1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Along with advancement in miniaturization technologies, highly scaled high-speed semiconductor devices with a gate length less than 50 nm have been realized.
In such a highly scaled high-speed transistor, the area of the channel region below the gate electrode is very small, and the electron mobility or hole mobility across the channel region is greatly influenced by a stress applied to the channel region. Many research and study efforts have been made to optimize the stress applied to a channel region to improve the operational speed of the semiconductor device. See, for example, JP 2007-123439 A, or Mayuzumi, S., et al., IEEE Trans Electron Devices Vol. 56, No. 4, pp. 620-626, 2009.
To improve the operating speed of an re-channel MOS transistor, a technique of forming a tensile stress layer in the device region of the re-channel MOS transistor so as to cover the gate electrode is well-known. This structure can improve the electron mobility across the channel region.
For a p-channel MOS transistor, a compressive stress layer is formed in the device region of the p-channel MOS transistor so as to cover the gate electrode to improve hole mobility across the channel region.
In the n-channel MOS transistor, the tensile stress layer induces tensile strain in the channel region in the direction of gate length. As a result, the electron mobility, and accordingly, the operating speed of the n-channel MOS transistor increase.
In the p-channel MOS transistor, the compressive stress induces compressive strain in the channel region along the channel direction. As a result, the hole mobility in the channel increases, accordingly the operating speed of the p-channel MOS transistor increases.
With a conventional n-channel or p-channel MOS transistor, the stress layer formed for the corresponding gate electrode extends on the silicon substrate near the channel region. In the area near the channel region of, for example, n-channel MOS transistor, a tensile stress acts directly on the surface of the silicon substrate. Similarly, in the area near the channel region of the p-channel MOS transistor, a compressive stress acts directly on the surface of the silicon substrate.
However, in the conventional n-channel transistor and p-channel MOS transistor, the tensile stress layer and the compressive stress layer are attached to the side walls of the corresponding gate electrodes. For this reason, the tensile stress or the compressive stress cannot be efficiently transferred to the silicon substrate.